Long term, the safety core becomes a purpose-built chip: a mask ROM for the commandments, lockstep cores, its own sensing and a safe-torque-off driver on one die. It is a research programme that runs beside the ZIV prototype and never blocks it.
Hover or tap a block. Illustrative floorplan of the research concept. Not a fabricated design.
Commandments in mask ROM cannot be rewritten by an attacker with remote access.
Its own clock, memory, sensing and drive cut-off. The AI stack cannot starve or confuse it.
No operating system or scheduler between a hazard and a stop. That makes safety cases easier to build.
Mask ROM guarantees the rules are the rules we shipped. It does not stop an attacker with physical access from glitching power or clock to make the chip skip a check. Voltage-glitch attacks have defeated hardware roots of trust in production vehicles.
So the design adds the defences that matter in that case:
Our claim is narrower and true: remote or software compromise of the AI stack cannot reach the safety core.
A certified-class safety microcontroller and safety relay on the ZIV prototype. The safety core exists in hardware from day one.
The Core logic on an FPGA to prove the architecture, fault injection and timing before committing to a mask.
A small multi-project-wafer test chip on a mature node to validate the ROM, lockstep and monitors.
A production safety chip, after pilots and funding justify the cost of a full mask set.
We are evaluating open RISC-V cores such as SHAKTI and Indian multi-project-wafer routes. Nothing here is committed or funded yet.
We are looking for academic and industry partners for the research track.